1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, the invention relates to a semiconductor device comprising MOS (metal oxide semiconductor) transistors and a method for manufacturing that semiconductor device.
2. Description of the Background Art
FIGS. 4A through 4F are cross-sectional views showing structures of conventional MOS transistors and steps to fabricate such transistors. These steps constitute a method for producing MOS transistors containing within their gate electrodes a stacked film made of tungsten silicide (WSi) and polysilicon, i.e., MOS transistors in a WSi-polycide structure. The steps also make up a method for having NMOS transistors and PMOS transistors formed adjacent to one another on a single substrate.
Conventionally, as shown in FIG. 4A, isolation regions 12 are first formed to a depth of 4,000 angstroms by use of an insulating film such as an oxide film on a silicon substrate 10. The isolation regions 12 are laid out so as to isolate NMOS and PMOS regions (where NMOS and PMOS transistors are to be formed respectively) from one another on the silicon substrate 10 (step 1).
The silicon substrate 10 is arranged so that the NMOS regions will serve as P-type semiconductors and PMOS regions as N-type semiconductors (step 2).
On the surface of the silicon substrate 10, a silicon oxide film 14 to be used later as a gate insulating film is formed to a thickness of 40 angstroms (step 3).
On the silicon oxide film 14, polysilicon is deposited by low-pressure CVD. This forms a polysilicon film 16 having a thickness of 1,000 angstroms (step 4).
On the polysilicon film 16, a resist film 18 is patterned so as to expose the NMOS regions while covering the PMOS regions (step 5).
With the resist film 18 used as a mask, N-type impurities consisting of phosphorus (P) are injected at 10 keV with a density of 8xc3x971015 atoms/cm2 into the NMOS regions of the polysilicon film 16 (step 6).
As depicted in FIG. 4B, a resist film 20 is patterned so as to expose the PMOS regions while covering the NMOS regions on the polysilicon film 16 (step 7).
Then with the resist film 20 used as a mask, P-type impurities consisting of BF2 are injected at 10 keV with a density of 6xc3x971015 atoms/cm2 into the PMOS regions of the polysilicon film 16 (step 8).
As indicated in FIG. 4C, a WSi film 22 with a thickness of 1,000 angstroms is formed on the polysilicon film 16 (step 9).
On the WSi film 22, a resist film 24 is patterned so as to expose the NMOS regions while covering the PMOS regions (step 10).
With the resist film 24 used as a mask, N-type impurities consisting of phosphorus (P) are injected at 30 keV with a density of 2xc3x971015 atoms/cm2 into the NMOS regions of the WSi film 22 (step 11).
As shown in FIG. 4D, a resist film 26 is patterned on the WSi film 22 so as to expose the PMOS regions while covering the NMOS regions (step 12).
With the resist film 26 used as a mask, P-type impurities consisting of boron (B) are injected at 10 keV with a density of 4xc3x971015 atoms/cm2 into the PMOS regions of the WSi film 22 (step 13).
On the WSi film 22, as depicted in FIG. 4E, a silicon oxide film 28 with a thickness of 1,000 angstroms is formed (step 14).
Thereafter, a silicon nitride film 30 with a thickness of 500 angstroms is formed on the silicon oxide film 28 (step 15).
On the silicon nitride film 30, a resist film 32 is formed. The resist film 32 thus furnished is patterned into gate electrodes by photolithography (step 16).
As indicated in FIG. 4F, the silicon nitride film 30 is patterned into gate electrodes by etching, with the resist film 32 used as a mask (step 17).
The silicon nitride film 30 thus patterned is used as a mask for anisotropic etching whereby the silicon oxide film 28, WSi film 22, polysilicon film 16 and silicon oxide film 14 are patterned successively into gate electrodes (step 18).
N-type impurities are injected into the NMOS regions of the silicon substrate in order to form LDD (Lightly Doped Drain) regions. P-type impurities are injected into the PMOS regions of the substrate to form the same type of regions (step 19).
An insulating film such as a silicon oxide film is deposited all over the wafer. The insulating film thus furnished is subjected to anisotropic etching whereby sidewalls 33 protecting the sides of the gate electrodes are formed (step 20).
N-type impurities are injected into the NMOS regions of the silicon substrate in order to form source and drain regions of the NMOS transistors. P-type impurities are injected into the PMOS regions of the substrate to form source and drain regions of the PMOS transistors (step 21).
As described, the conventional manufacturing method involves injecting N-type impurities (such as phosphorus) or P-type impurities (B, BF2, etc.) are injected into the polysilicon film 16 and WSi film 22. The injected impurities are later activated by suitable heat treatments to contribute significantly to providing electric conduction. polysilicon film 16 and WSi film 22. The injected impurities are later activated by suitable heat treatments to contribute significantly to providing electric conduction.
In recent years, diversification of data processing applications has entailed the development of system LSIs that combine a semiconductor memory with a logic LSI. For example, an eDRAM (embedded DRAM) combining a DRAM (Dynamic Random Access Memory) with a logic LSI is known as a system LSI capable of processing massive image data at high speed.
Steps for combining a DRAM with a logic LSI to fabricate a system LSI (eDRAM) may sometimes involve numerous heat treatments following the formation of MOS transistors to be included in the system LSI. During such heat treatments, impurities in the gate electrodes of the MOS transistors can diffuse into a gate insulating film or like components, resulting in a reduced density of impurities in the gate electrodes.
Such a drop in the impurity density of the gate electrodes or a sustained inactive state of the impurities in the electrodes may lead to a depletion layer in the electrodes getting inordinately large in proportion, a phenomenon called gate electrode depletion. The diffusion of impurities in the gate electrodes (gate electrode depletion) can trigger changes in MOS transistor characteristics. For these reasons, the conventional method has been associated with the problem of fluctuating MOS transistor characteristics, especially when applied to the fabrication of the system LSI.
It is therefore a first object of the present invention to overcome the above and other deficiencies of the prior art and to provide MOS transistors capable of exerting their required characteristics after undergoing heat treatments during DRAM fabrication processes.
It is a second object of the present invention to provide a method suitable for manufacturing the inventive MOS transistors.
The above objects of the present invention are achieved by a semiconductor device described below. The semiconductor device includes a silicon substrate. A gate insulating film is formed on the silicon substrate. A gate electrode is formed on the gate insulating film. The gate electrode includes an amorphous silicon film formed on the gate insulating film, a tungsten silicide film formed on the amorphous silicon film, and an insulating film formed on the tungsten silicide film.
The above objects of the present invention are also achieved by A method for manufacturing a semiconductor device including MOS transistors. In the manufacturing method, an isolation region is formed on a silicon substrate so as to isolate a plurality of MOS regions in which to form MOS transistors. A first insulating film is formed as a gate insulating film on the silicon substrate. An amorphous silicon film is formed on the first insulating film. A tungsten silicide film is formed on the amorphous silicon film. A second insulating film is formed on the tungsten silicide film. The first insulating film, the amorphous silicon film, the tungsten silicide film, and the second insulating film are patterned into gate electrodes.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.